This sets of mcq most on digital design and issues, Moore and Mealy machines in vlsidt...
SET 1 of Digital design and Issues MCQ
1. Which is the delay components in sequential system?
a) AND gates
b) Flip-flops
c) OR gates
d) XOR gates
Answer:-b) Flip-flops
2. What is a shift register that will accept a parallel input and can shift data left or right called?
a) bidirectional universal
b) PISO
c) tri-state
d) SIPO
Answer:-a) bidirectional universal
3. In moore machine, the O/P depends upon?
a) Current State
b) Previous State
c) State and Input
d) Only Input
Answer:-a) Current State
4. In mealy machine, the O/P depends upon?
a) Current State
b) Previous State
c) Only Input
d) State and Input
Answer:-d) State and Input
5. For a give Moore Machine, Given Input=’111011’, thus the output would be of length:
a) |Input-1|
b) |Input|
c) |Input|+1
d) Cannot be predicted
Answer:-c) |Input|+1
6) What happens if the input is low in FSM ?
a) No transition in state
b) Remains in a single state
c) Change of state
d) Invalid state
Answer:-a) No transition in state
7) In Gray coding, when the state machine changes state, ______ bit/s in the state vector changes the value.
a) one
b) two
c) four
d) eight
Answer:-a) one
8) CASE is a sequential statement, which is similar to _________ concurrent statement.
a) WHEN
b) PORT MAP
c) Concurrent assignment
d) THEN
Answer:-a)WHEN
9) A common error with programming flip-flops is accidentally making a _______.
a) Logic Gate
b) Driver
c) Latch
d) NAND gate
Answer:-c) Latch
10) why is the use of mode buffer prohibited in the design process of synthesizer ?
a) Because Maximum ASIC vendors fail to support mode buffer in libraries
b) Because critical path has preference in placement
c) To avoid mixing of clock edges
d) To prevent the occurrence of glitches and metastability
Answer:-a) Because Maximum ASIC vendors fail to support mode buffer in libraries
SET 2 Digital design and Issues MCQ
11. Which one is true about metastability ?
a) it enters a state where its output is not predictable:
b) there are setup and hold time violations in any flip-flop
c) the flip-flop settles down to either '1' or '0'.
d) all of the above
Answer:-d) all of the above
12. The Higher Noise Margin is given by:
a) VIH ~ VOH(Difference between VIH and VOH, depends on which one is greater)
b) VIH – VOH
c) VOH – VIH
d) All of the mentioned
Answer:-c) VOH – VIH
13) A 4-input OR gate has a fan-out of
a) 1
b) 4
c) 8
d) None of the above
Answer:-a) 1
14) A 8-input AND gate has a fan-in of
a) 1
b) 4
c) 8
d) None of the above
Answer:-c) 8
15. Delay between shortest path and longest path in the clock is called as ____.
a. Useful skew
b. Local skew
c. Global skew
d. Slack
Answer:-c. Global skew
16. What is dynamic hazard?
a. The transient pulse during a 1-to-0 transition
b. The transient pulse during a 0-to-1 transition
c. The transient pulse on a signal line whose value does not change
d. Both A and B
17. How to Reduce Ground Bounce
a) Use Decoupling Capacitors to Localize Ground Bounce
b) Use Resistors to Limit Current Flow
c) Use Routing to Reduce Inductance
d) All of the above
Answer:-d) All of the above
18. Which of the given logic family provide minimum power dissipation
a) JFET
b) ECL
c) CMOS
d) TTL
Answer:-c) CMOS
19. In CMOS domino logic------------- is used
a) one phase clock
b) two phase clock
c) three phase clock
d) four phase clock
Answer:-a) one phase clock
VlsiDT design mcq for online exams part 1
