Some Microcontroller important MCQ's questions for university exams, Placements, companies exams, GATE and other exams preparations with answers.
1) Which digital operations are performed over the detected mismatch outputs with an intention to
generate a single output RB port change output?
a. OR
b. AND
c. EX-OR
d. NAND
ANSWER: OR
2) When does it become feasible for portB pins (RB4 to RB7) to support its unique feature of
'interrupt on change'?
a. By configuring all the pins (RB4-RB7) as inputs
b. By configuring all the pins (RB4-RB7) as outputs
c. By configuring any one of the pins as inputs
d. By configuring any one of the pins as outputs
ANSWER: By configuring all the pins (RB4-RB7) as inputs
3) Which bit/s should be necessarily cleared in OPTION (SFR) register in order to turn on the weak
internal pull-ups of port B?
a. RPO
b. RPBU
c. RBIF
d. All of the above
ANSWER: RPBU
4) When does it become possible for a bit to get accessed from bank '0' in the direct addressing
mode of PICs?
a. Only when RPO bit is set 'zero'
b. Only when RPO bit is set '1'
c. Only when RPO bit is utilized along with 7 lower bits of instruction code
d. Cannot Predict
ANSWER: Only when RPO bit is set 'zero'
5) Which bit permits to enable (if set) or disable (if cleared) all the interrupts in an INTCON register?
a. GIE
b. ADIE
c. RBIE
d. TOIE
ANSWER: GIE
6) Where is the exact specified location of an interrupt flag associated with analog-to-digital
converter?
a. INTCON
b. ADCON0
c. ADRES
d. PCLATH
ANSWER: ADCON0
7) Where are the prescalar assignments applied with a usage of PSA bit?
a. Only RTCC
b. Only Watchdog timer
c. Either RTCC or Watchdog timer
d. Neither RTCC nor Watchdog timer
ANSWER: Either RTCC or Watchdog timer
8) Which bit of OPTION register has a potential to decide the falling or rising edge sensitivity for the
external interrupt INT?
a. RBPU
b. INTEDG
c. PSA
d. RTS
ANSWER: INTEDG
9) Which bank of RFS has a provision of addressing the status register?
a. Only Bank 1
b. Only Bank 2
c. Either Bank 1 or Bank 2
d. Neither Bank 1 nor Bank 2
ANSWER: Either Bank 1 or Bank 2
10) Which register acts as an input-output control as well as data direction register for PORTA in
bank 2 of RFS?
a. INDF (80H)
b. TRISB (85H)
c. TRISA (85H)
d. PCLATH (8A)
ANSWER: TRISA (85H)
11) Which among the below specified registors are addressable only from bank1 of RFS?
a. PORTA (05H)
b. PORTB (06H)
c. FSR (04H)
d. ADCON0 (07H)
ANSWER: PORTA (05H)
12) Which registers are adopted by CPU and peripheral modules so as to control and handle the
operation of device inhibited in RFS?
a. General Purpose Register
b. Special Purpose Register
c. Special Function Registers
d. All of the above
ANSWER: Special Function Registers
13) How many bits are utilized by the instruction of direct addressing mode in order to address the
register files in PIC?
a. 2
b. 5
c. 7
d. 8
ANSWER: 7
14) When do the special address 004H get automatically loaded into the program counter?
a. After the execution of RESET action in program counter
b. After the execution of 'goto Mainline ' instruction in the program memory
c. At the occurrence of interrupt into the program counter
d. At the clearance of program counter with no value
ANSWER: At the occurrence of interrupt into the program counter
15) What location is attributed to 'goto Mainline' instruction in the program memory of PIC 16C61?
- Published on 12 Nov 15
a. 000H
b. 004H
c. 001H
d. 011H
ANSWER: 000H
16) How many bits are required for addressing 2K & 4K program memories of PIC 16C61
respectively?
a. 4 & 8 bits
b. 8 & 16 bits
c. 11 & 12 bits
d. 12 & 16 bits
ANSWER: 11 & 12 bits
17) What is the executable frequency range of High speed (HS) clocking method by using cystal/
ceramic/ resonator or any other external clock source?
a. 0-4 MHz
b. 5-200 KHz
c. 100kHz- 4 MHZ
d. 4-20 MHz
ANSWER: 4-20 MHz
18) Which significant feature/s of crystal source contribute/s to its maximum predilection and utility
as compared to other clock sources?
a. High accuracy
b. Proficiency in time generation
c. Applicability in real-time operations
d. All of the above
ANSWER: All of the above
19) Which form of clocking mechanism is highly efficient and reliable for crystal or ceramic clock
sources for operating at the range of 5- 200 kHz in PIC?
a. RC
b. LP (Low-Power Clocking)
c. XT
d. HS (High Speed)
ANSWER: LP (Low-Power Clocking)
20) What happens when the supply voltage falls below 4V during the power-up timer delay of 72ms in
PIC?
a. CPU resets PIC once again in BOR mode
b. BOR reset mode gets disabled
c. PIC does not remain in BOR mode until the voltage increases irrespective of stability
d. Power-up timer kills 72ms more again
ANSWER: CPU resets PIC once again in BOR mode
21) Which crucial feature/function of Brown-Out-Reset (BOR) makes the PIC to be completely unique
and distinct from other microcontrollers?
a. It can reset the PIC automatically in running condition
b. It can reset the PIC even when the supply voltage increases above 4V
c. It can reset the PIC without enabling the power-up timer
d. All of the above
ANSWER: It can reset the PIC automatically in running condition
22) What output is generated by OSC2 pin in PIC oscillator comprising RC components for
sychronizing the peripherals with PIC microcontroller?
a. (1/2) x frequency of OSC1
b. (1/4) x frequency of OSC1
c. (1/8) x frequency of OSC1
d. (1/16) x frequency of OSC1
ANSWER: (1/8) x frequency of OSC1
23) Which among the below mentioned PICs do not support the Brown-Out-Reset (BOR) feature?
a. PIC 16C66
B. PIC 16C74
C. PIC 16C61
D. PIC 16C71
a. A & B
b. C & D
c. A & C
d. B & D
ANSWER: C & D
24) When does it become very essential to use the external RC components for the reset circuits?
a. Only if initialization is necessary for RAM locations
b. Only if VDD power-up slope is insufficient at a requisite level
c. Only if voltage drop exceeds beyond the limit
d. Only if current limiting factor increases rapidly
ANSWER: Only if VDD power-up slope is insufficient at a requisite level
25) Which program location is allocated to the program counter by the reset function in Power-onReset (POR) action modes?
a. Initial address
b. Middle address
c. Final address
d. At any address reliable for reset operations
ANSWER: Initial address
26) What is the purpose of using the start-up timers in an oscillator circuit of PIC?
a. For ensuring the inception and stabilization of an oscillator in a proper manner
b. For detecting the rise in VDD
c. For enabling or disabling the power-up timers
d. For generating the fixed delay of 72ms on power-up timers
ANSWER: For ensuring the inception and stabilization of an oscillator in a proper manner
27) Which kind of mode is favourable for MCLR pin for indulging in reset operations?
a. Normal mode
b. Sleep mode
c. Power-down mode
d. Any flexible mode
ANSWER: Sleep mode
28) What is the rate of power up delay provided by an oscillator start-up timer while operating at XT,
LP and HS oscillator modes?
a. 512 cycles
b. 1024 cycles
c. 2048 cycles
d. 4096 cycles
ANSWER: 1024 cycles
29) Generation of Power-on-reset pulse can occur only after __________
a. the detection of increment in VDD from 1.5 V to 2.1 V
b. the detection of decrement in VDD from 2.1 V to 1.5 V
c. the detection of variable time delay on power up mode
d. the detection of current limiting factor
ANSWER: the detection of increment in VDD from 1.5 V to 2.1 V
30) Which condition/s of MCLR (master clear) pin allow to reset the PIC?
a. High
b. Low
c. Moderate
d. All of the above
ANSWER: Low
31) Where do the contents of PCLATH get transferred in the higher location of program counter while
writing in PCL (Program Counter Latch)?
a. 11th bit
b. 12th bit
c. 13th bit
d. 14th bit
ANSWER: 13th bit
32) Which among the below stated registers specify the address reachability within 7 bits of address
independent of RP0 status bit register?
a. PCL
b. FSR
c. INTCON
d. All of the above
ANSWER: All of the above
33) Which statement is precise in relation to FSR, INDF and indirect addressing mode?
a. Address byte must be written in FSR before executing INDF instruction in indirect addressing
mode
b. Address byte must be written in FSR after executing INDF instruction in indirect addressing mode
c. Address byte must be written in FSR at the same time during the execution of INDF instruction in
indirect addressing mode
d. Address byte must be always written in FSR as it is independent of any instruction in indirect
addressing mode
a. Only A
b. Only B
c. Only A & B
d. A & D
ANSWER: Only A
34) Which status bits exhibit carry from lower 4 bits during 8-bit addition and are especially beneficial
for BCD addition?
a. Carry bit (C)
b. Digits Carry bit (DC)
c. Both a & b
d. None of the above
ANSWER: Digits Carry bit (DC)
35) The RPO status register bit has the potential to determine the effective address of______
a. Direct Addressing Mode
b. Indirect Addressing Mode
c. Immediate Addressing Mode
d. Indc. Watchdog Timer (WDT) exed Addressing Mode
ANSWER: Direct Addressing Mode
36) Which among the below mentioned bits specify the reset status of register in readable format and
are usually utilized in sleep mode of PIC?
a. TO
b. PD
c. Both a & b
d. None of the above
ANSWER: Both a & b
37) How many RPO status bits are required for the selection of two register banks?
a. 1
b. 2
c. 8
d. 16
ANSWER: 1
38) Which register/s is/are mandatory to get loaded at the beginning before loading or transferring the
contents to corresponding destination registers?
a. W
b. INDF
c. PCL
d. All of the above
ANSWER: W
39) Which among the CPU registers of PIC 16C6X/7X is not 8-bit wide?
a. Status Register
b. Program Counter Latch (PCLATH) Register
c. Program Counter Low Byte (PCL) Register
d. File Selection Register (FSR)
ANSWER: Program Counter Latch (PCLATH) Register
40) Which timer/s possess an ability to prevent an endless loop hanging condition of PIC along with
its own on-chip RC oscillator by contributing to its reliable operation?
a. Power-Up Timer (PWRT)
b. Oscillator Start-Up Timer (OST)
c. Watchdog Timer (WDT)
d. All of the above
ANSWER: Watchdog Timer (WDT)
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