1) Which bits of opcode specify the type of registers to be used in the register addressing mode?
a. LSB
b. MSB
c. Both a & b
d. None of the above
ANSWER: LSB
2) Which byte has the capability to interrupt the slave when SM2 bit is assigned to be '1' after the
initialization process in the multiprocessor mode of communication?
a. Address byte
b. Data byte
c. Both a & b
d. None of the above
ANSWER: Address byte
3) How does it become possible for 9th bit to differentiate the address byte from the data byte
during the data transmission process in multiprocessor communication?
a. By recognizing 9th bit as '1' for address byte & '0' for data byte
b. By recognizing 9th bit as '0' for address byte & '1' for data byte
c. By recognizing 9th bit as '1' for address as well as data bytes
d. By recognizing 9th bit as '0' for address as well as data bytes
ANSWER: By recognizing 9th bit as '1' for address byte & '0' for data byte
4) Which serial modes possess the potential to support the multi-processor type of
communication?
a. Modes 0 & 1
b. Modes 1 & 2
c. Modes 2 & 3
d. All of the above
ANSWER: Modes 2 & 3
5) How is the baud rate determined on the basis of system clock frequency (fsc) in accordance to
mode '0' of serial communication?
a. (oscillator frequency) / 12
b. [2SMOD / 32] x (oscillator frequency) / [12 x (256 – (TH1)]
c. [2SMOD / 64] x (oscillator frequency)
d. 2SMOD/ 32 x (Timer 1 overflow rate)
ANSWER: (oscillator frequency) / 12
6) Which pin in the shift register mode (Mode 0) of serial communication allow the data
transmission as well as reception?
a. TXD
b. RXD
c. RB8
d. REN
ANSWER: RXD
7) What is the bit transmitting or receiving capability of mode 1 in serial communication?
a. 8 bits
b. 10 bits
c. 11 bits
d. 12 bits
ANSWER: 10 bits
8) Which two bits are supposed to be analyzed/tested for unity value (1) in SCON for the reception
of byte in mode 1 serial communication?
a. RI & TI
b. REN & RB8
c. RI & REN
d. TI & RB8
ANSWER: RI & REN
9) Which bits exhibit and signify the termination phase of the character transmission and reception
in SCON special function register?
a. Control bits
b. Status bits
c. Both a & b
d. None of the above
ANSWER: Status bits
10) Which factor/s is/are supposed to have the equal values at both phases of transmission and
reception levels with an intimation of error-free serial communication?
a. Baud Rate
b. Number of data bits & stop bits
c. Status of Parity bits
d. All of the above
ANSWER: All of the above
11) Why is it not necessary to specify the baud rate to be equal to the number of bits per second?
a. Because each bit is preceded by a start bit & followed by one stop bit
b. Because each byte is preceded by a start byte & followed by one stop byte
c. Because each byte is preceded by a start bit & followed by one stop bit
d. Because each bit is preceded by a start byte &followed by one stop byte
ANSWER: Because each byte is preceded by a start bit & followed by one stop bit
12) Which among the below mentioned sequence of program instructions represent the correct
chronological order for the generation of 2kHz square wave frequency?
1. MOV TMOD, 0000 0010 B
2. MOV TL0, # 06H
3. MOV TH0, # 06H
4. SETB TR0
5. CPL p1.0
6. ORG 0000H
a. 6, 5, 2, 4, 1, 3
b. 6, 1, 3, 2, 4, 5
c. 6, 5, 4, 3, 2, 1
d. 6, 2, 4, 5, 1, 3
ANSWER: 6, 1, 3, 2, 4, 5
13) What is the maximum delay generated by the 12 MHz clock frequency in accordance to an autoreload mode (Mode 2) operation of the timer?
a. 125 μs
b. 250 μs
c. 256 μs
d. 1200 μs
ANSWER: 256 μs
14) Consider the below generated program segment for initializing Timer 1 in Mode 1 operation :
MOV SP, # 54 H
MOV TMOD ,# 0010 0000 C
SET C ET1
SETC TR0
SJMP $
Which among the below mentioned program segments represent the correct code?
- Published on 09 Nov 15
a. MOV SP, # 54 H
MOV TCON ,# 0010 0000 C
SETC ET1
SETC TR0
SJMP $
b. MOV SP, # 54H
MOV TMOD ,# 0010 0000 C
SETC ET0
SETC TR0
SJMP $
c. MOV SP, # 54 H
MOV TMOD ,# 0010 0000 C
SETC ET1
SETC TR1
SETC EA
SJMP $
d. MOV SP, # 54 H
MOV TMOD ,# 0010 0000 C
SETC ET0
SETC TR1
SETC EA
SJMP $
ANSWER: MOV SP, # 54 H
MOV TMOD ,# 0010 0000 C
SETC ET1
SETC TR1
SETC EA
SJMP $
15) Which timer mode exhibit the necessity to generate the interrupt by setting EA bit in IE
enhancing the program counter to jump to another vector location?
a. Mode 0
b. Mode 1
c. Mode 2
d. Mode 3
ANSWER: Mode 1
16) Which among the following control/s the timer1 especially when it is configured as a timer in
mode'0', where gate and TR1 bits are attributed to be '1” in TMOD register?
a. TR1
b. External input at (INT1)
c. TF1
d. All of the above
ANSWER: External input at (INT1)
17) Which bit must be set in TCON register in order to start the 'Timer 0' while operating in 'Mode 0'?
a. TR0
b. TF0
c. IT0
d. IE0
ANSWER: TR0
18) How many machine cycle/s is/are executed by the counters in 8051 in order to detect '1' to '0'
transition at the external pin?
a. One
b. Two
c. Four
d. Eight
ANSWER: Two
19) Which special function register play a vital role in the timer/counter mode selection process by
allocating the bits in it?
a. TMOD
b. TCON
c. SCON
d. PCON
ANSWER: TMOD
20) What is the counting rate of a machine cycle in correlation to the oscillator frequency for timers?
a. 1 / 10
b. 1 / 12
c. 1 / 15
d. 1 / 20
ANSWER: 1 / 12
21) Which among the below mentioned reasons is/are responsible for the generation of Serial Port
Interrupt?
a. Overflow of timer/counter 1
b. High to low transition on pin INT1
c. High to low transition on pin INT0
d. Setting of either TI or RI flag
a. A & B
b. Only B
c. C & D
d. Only D
ANSWER: Only D
22) What kind of triggering configuration of external interrupt intimate the signal to stay low until the
generation of subsequent interrupt?
a. Edge-Triggering
b. Level Triggering
c. Both a & b
d. None of the above
ANSWER: Level Triggering
23) Match the following :
a. ISS ----------------------------- 1. Monitors the status of interrupt pin
b. IER ----------------------------- 2. Allows the termination of ISS
c. RETI --------------------------- 3. MCS-51 Interrupts Initialization
d. INTO -------------------------- 4. Occurrence of high to low transition level
a. A-1, B-2, C-3, D-4
b. A-3, B-2, C-4, D-1
c. A-1, B-3, C-2, D-4
d. A-4, B-3, C-2, D-1
ANSWER: A-1, B-3, C-2, D-4
24) Which location specify the storage/loading of vector address during the interrupt generation?
a. Stack Pointer
b. Program Counter
c. Data Pointer
d. All of the above
ANSWER: Program Counter
25) Which address/location in the program memory is supposed to get occupied when CPU jump
and execute instantaneously during the occurrence of an interrupt?
a. Scalar
b. Vector
c. Register
d. All of the above
ANSWER: Vector
26) How does the processor respond to an occurrence of the interrupt?
a. By Interrupt Service Subroutine
b. By Interrupt Status Subroutine
c. By Interrupt Structure Subroutine
d. By Interrupt System Subroutine
ANSWER: By Interrupt Service Subroutine
27) Consider the following statements. Which of them is/are correct in case of program execution
related to program memory?
a. External Program memory execution takes place from 1000H through 0FFFFH only when the status
of EA pin is high (1)
b. External Program memory execution takes place from 0000H through 0FFFH only when the status of
EA pin is low (0)
c. Internal Program execution occurs from 0000H through 0FFFH only when the status of EA pin is
held low (0)
d. Internal program memory execution occurs from 0000H through 0FFFH only when EA pin is held
high (1)
a. A & C
b. B & D
c. A & B
d. Only A
ANSWER: B & D
28) What is the divisional range of program memory for internal and external memory portions
respectively when enable access pin is held high (unity)?
a. 0000H - 0FFFH & 1000H - FFFFH
b. 0000H - 1000H & 0FFFH - FFFFH
c. 0001H - 0FFFH & 01FFH - FFFFH
d. None of the above
ANSWER: 0000H - 0FFFH & 1000H - FFFFH
29) What is the bit addressing range of addressable individual bits over the on-chip RAM?
a. 00H to FFH
b. 01H to 7FH
c. 00H to 7FH
d. 80H to FFH
ANSWER: 00H to 7FH
30) The upper 128 bytes of an internal data memory from 80H through FFH usually represent
_______.
a. general-purpose registers
b. special function registers
c. stack pointers
d. program counters
ANSWER: special function registers
