This sets of mcq on VHDL design questions with answers for your next online exams...
Read this VlsiDT design mcq for online exams Part-1
SET 1 of VHDL design MCQ
1. Which of the following is an abstraction of the signal voltage?
a) level
b) strength
c) nature
d) size
Ans - a
2. Which wait statement does follow a condition?
a) wait for
b) wait until
c) wait
d) wait on
Ans - b
3. How many kinds of wait statements are available in the VHDL design?
a) 3
b) 4
c) 5
d) 6
Ans - a
4. Which of the following VHDL design units contain the description of the circuit?
a) Configurations
b) Architecture
c) Library
d) Entity
Ans - b
5. WAIT statement can’t appear under _______ directly.
a) Architecture
b) Process
c) Procedure
d) Subprogram
Ans - a
6. WAIT UNTIL statements cause the process to wait ________
a) When a signal changes value
b) Until a condition is true
c) For a specific time period
d) When either a signal changes its value or a condition comes true
Ans - b
7. In case of sensitivity list the process suspends at the end of the process and in WAIT statement it suspends ____________
a) At the beginning
b) At the end
c) At the beginning of architecture
d) Where the WAIT statement is encountered
Ans - d
8. How to declare a constant in VHDL?
a) CONSTANT name : type := value;
b) CONSTANT name := value;
c) CONSTANT name := type := value;
d) CONSTANT name := type : value;
Ans - a
9. Which of the following is local to the block in which it is declared?
a) Signal
b) Integer
c) Constant
d) Variable
Ans - d
10. What is the scope of a constant declared in an entity?
a) Local to the entity
b) Global to the whole code
c) Local to the port
d) Global to the entity and all the architecture associated
Ans - c
SET 2 VHDL design MCQ
11. Which of the following is the default type of ports of an entity?
a) Variables
b) Constants
c) Signals
d) Functions
Ans - d
12. When there is no delay specified in a signal assignment (concurrent), the delay will be _______
a) Zero
b) Transport delay
c) Inertial delay
d) Delta delay
Ans - b
13. Which of the following is true about packages?
a) Package is collection of libraries
b) Library is collection of packages
c) Package is collection of entities
d) Entity is collection of packages
Ans - b
14. Any item declared in a package declaration section are visible to _______
a) Every design unit
b) Package body only
c) Library containing that package
d) Design unit that USE the package
Ans - d
15. If a user wants to include his/her own package in the body, which library he/she must use?
a) STD
b) IEEE
c) WORK
d) STD_LOGIC
Ans - c
16. Among the four packages given below, which is the most used package of VHDL?
a) STD_LOGIC_1164
b) TEXTIO
c) STD_LOGIC_ARITH
d) NUMERIC_STD
Ans - a
17. The STD_LOGIC_1164 package is contained by _______ library.
a) STD
b) WORK
c) STD_LOGIC
d) IEEE
Ans - d
18. A function is a ________ code.
a) Concurrent
b) Sequential
c) Concurrent as well as sequential
d) Process oriented
Ans - b
19. The parameters used at the time of function call are called _________
a) Formal parameters
b) Actual parameters
c) Real parameters
d) Complex parameters
Ans - b
20. What is the use of resolution functions?
a) Return the value of a signal with multiple drivers
b) Resolve value of a constant with multiple drivers
c) Convert one data type into another
d) Convert one data object into another
Ans - a
Read this VlsiDT design mcq for online exams Part-1
