This sets of mcq contains questions on VlsiDT design for preparing online exams..
SET 1 of vlsidt design mcq
1. Identify the correct Syntax
a) USE library_name.package_name.package_parts;
b) USE library_name.package_name ;
c) USE package_name.package_parts ;
d) USE library_name. package_parts ;
Ans - a
2. Which package defines a set of arithmetic, conversion, and comparison functions for SIGNED, UNSIGNED, SMALL_INT, INTEGER, STD_ULOGIC, STD_LOGIC, and STD_LOGIC_VECTOR.
a) IEEE.NUMERIC_STD.all
b) IEEE.STD_LOGIC_ARITH.all
c) IEEE.STD_LOGIC_SIGNED.all
d) IEEE.STD_LOGIC_UNSIGNED.all
Ans - b
3. Architecture specifies
a) Behaviour
b) Function
c) Relationship between inputs and outputs of an entity
d) All of the above
Ans - d
4. Since a number of architectures can exist for an entity, using which statement we can bind a particular architecture to the entity
a) Concurrent
b) Configuration
c) Sequential
d) Process
Ans - b
5. Which of the characteristics is true for VHDL Language
a) strongly typed language
b) not case sensitive
c) supports a wide variety of data types and operators
d) All of the above
Ans - d
6. The name given to the object is called __________
a) Reserved Keyword
b) Identifier
c) Signal
d) variable
Ans - b
7. TYPE matrix2D IS ARRAY (0 TO 3, 7 DOWNTO 0 ) OF STD_LOGIC . This syntax will generate _______________
a) 1D array
b) 2D array
c) 1D X 1D
d) None of the above
Ans - b
8. VHDL provides which of the above pre-defined operators
a) Assignment operators
b) Logical operators
c) Relational operators
d) All of the above
Ans - d
9. ___________ is used to connect design entities together and communicate changes in values within a design
a) Variable
b) Constant
c) Attribute
d) Signal
Ans - a
10. _________ can be declared and used inside the process statement only.
a) Variables
b) Signals
c) Constant
d) All of the above
Ans - a
SET 1 of vlsidt design mcq
11) ____________ is a static parameter that can be easily modified and adapted to different applications
a) Block
b) Generics
c) Ports
d) Buffer
Ans - b
12. “The output of the circuit depends solely on the current inputs”. This line stands true for
a) Combinational Logic
b) Sequential Logic
c) Both a and b
d) None of the above
Ans - a
13) Concurrent code is also called ____________code
a) dataflow code
b) behavioral code
c) Both a and b
d) None of the a and b
Ans - a
14) Conditional signal assignments are synthesized to generate
a) combinational logic
b) Sequential logic
c) None
d) All of the above
Ans - a
15. ______________ statement represents only a way of locally partitioning the code and makes the overall code more readable and more manageable
a) Generics
b) Functions
c) Block
d) Procedures
Ans - c
16. __________ is a concurrent statement used to create regular structures or conditional structures during elaboration and Used to create multiple copies of components, processes or blocks
a) Generate statement
b) Generics statement
c) Configuration statement
d) Block statement
Ans - a
17. ________________ modeling style is at the lowest level of abstraction where you have to first manually design the circuit.
a) Dataflow
b) Behavioral
c) Structural
d) None
Ans - c
18. Which of the following are examples of Sequential Statements
a) CASE statement
b) Loop statement
c) If-else statement
d) All of the above
Ans - d
19. Which of the following are capable of displaying output signal waveforms resulting from stimuli applied to the inputs?
a) VHDL simulator
b) VHDL emulator
c) VHDL debugger
d) VHDL locater
Ans - a
20. Which of the following describes the connections between the entity port and the local component?
a) port map
b) one-to-one map
c) many-to-one map
d) one-to-many maps
Ans - a
